Interconnect bus configured to implement multiple transfer proto

Details Interconnect bus configured to implement multiple transfer proto Interconnect bus configured to implement multiple transfer proto

1996-10-21

1998-06-30

Ray, Gopal C.

395308, 395306, 395286, G06F 1300

Patent

active

057746834

ABSTRACT:
A bus bridge includes a first bus port for coupling to a first expansion bus. The first bus implements a first transfer protocol compatible with the first bus port. The first bus port is adapted to couple through the first expansion bus to one or more peripheral devices. A second bus port couples to a second bus. The second bus implements a second transfer protocol compatible with the second bus port. The second bus port is adapted to couple through the second bus to one or more peripheral devices. The bus bridge is operable to implement the second transfer protocol on the second bus to communicate with one or more peripheral devices of a first type coupled to the second bus which are compatible with the second transfer protocol of the second bus. The bus bridge is further operable to implement a third transfer protocol on the second bus to communicate with one or more peripheral devices of a second type coupled to the second bus which are compatible with a third transfer protocol of a peripheral bus standard. The third transfer protocol of the peripheral bus standard is different from the second transfer protocol of the second bus. The bus bridge is operable to time multiplex transfers using the second transfer protocol of the second bus and the third transfer protocol of the peripheral bus standard on the second bus.

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PCI Local Bus Multimedia Design Guide, Revision 1.0, Mar. 29, 1994, pp. 1-40.
Peripheral Components, Intel, 1995, pp. ix, 1-1 through 1-72.

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