Sense amplifier, SRAM, and microprocessor

Details Sense amplifier, SRAM, and microprocessor Sense amplifier, SRAM, and microprocessor

1993-10-07

1996-07-09

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 51, 365205, G11C 700

Patent

active

055348009

ABSTRACT:
A sense amplifier for an SRAM providing both a small power consumption and a high speed sensing operation. The sense amplifier includes a first p-channel MOSFET having a source terminal connected to a bit line, a second p-channel MOSFET having a source terminal connected to another bit line, a first n-channel MOSFET having a drain terminal connected to a drain terminal of the first p-channel MOSFET and a gate terminal connected to a drain terminal of the second p-channel MOSFET and to a gate terminal of the first p-channel MOSFET, a second n-channel MOSFET having a drain terminal connected to a drain terminal of the second p-channel MOSFET, a gate terminal connected to a drain terminal of the first p-channel MOSFET and to a gate terminal of the second p-channel MOSFET, and a source terminal connected to a source terminal of the first n-channel MOSFET, a third p-channel MOSFET for controlling the connection/disconnection between a first power source (Vcc) and the drain terminal of the first p-channel MOSFET, a fourth p-channel MOSFET for controlling the connection/disconnection between the first power source Vcc and the drain terminal of the second p-channel MOSFET, and a third n-channel MOSFET for controlling the connection/disconnection between a second power source (ground) and the source terminals of the second n-channel MOSFETs.

REFERENCES:
patent: 4441771 (1984-04-01), Hoffmann
patent: 4567389 (1986-01-01), Van Tran
patent: 4616148 (1986-10-01), Ochii et al.
patent: 4651305 (1987-03-01), Davis
patent: 4680735 (1987-07-01), Miyamoto et al.
patent: 5243573 (1993-09-01), Makihara et al.
K. Sasaki et al, "A 9-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1219-1224.
S. Yamamoto, et al., "A 256K CMOS SRAM with Variable-Impedance Loads", ISSCC Digest of Technical Papers, Feb. 1985, pp. 58-59.
A. Sekiyama, et al., "A 1-V Operating 256-kb Full-CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 27, No. 5, May 1992, pp. 776-782.
Ootani et al., "A 4-Mb CMOS SRAM with a PMOS Thin-Film-Transistor Load Cell", IEEE Journal of Solid-State Circuits, vol.25, No. 5, Oct 1990, pp. 1082-1092.

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