Phase lock circuit for generating a phase synched synchronizing

Details Phase lock circuit for generating a phase synched synchronizing Phase lock circuit for generating a phase synched synchronizing

1989-10-24

1992-06-30

Envall, Jr., Roy N.

Facsimile and static presentation processing

Facsimile

Recording apparatus

358319, 358337, 360 371, H04N 593

Patent

active

051268540

ABSTRACT:
A phase lock circuit includes a control signal generator which generates a control signal changing for every frame consisting of an odd-numbered field and an even-numbered field in a reproduction mode. The control signal has a first level for a frame and a second level for a subsequent frame. The phase lock circuit further includes a first PLL circuit and a second PLL circuit. The first PLL circuit generates a first synchronizing signal which is phase-locked with a reproduced synchronizing signal for every other frame when the control signal is at the first level. The second PLL circuit generates a second synchronizing signal which is phase-locked with the reproduced synchronizing signal for every other frame when the control signal is at the second level. Furthermore, the phase lock circuit includes a select circuit which selects one of the first and second synchronizing signals supplied from the first and second PLL circuits on the basis of the control signal. The selected synchronizing signal is the synchronizing signal output from the phase lock circuit.

REFERENCES:
patent: 4420775 (1983-12-01), Yamazaki et al.
patent: 4542351 (1985-09-01), Okada
patent: 4613827 (1986-09-01), Takamori et al.
patent: 4616259 (1986-10-01), Moran et al.
patent: 4646103 (1987-02-01), Sugiyama et al.
patent: 4760468 (1988-07-01), Nakano et al.

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