Pipeline bus having registers and selector for real-time video s

Details Pipeline bus having registers and selector for real-time video s Pipeline bus having registers and selector for real-time video s

1990-07-23

1992-06-30

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 22, 358181, H04N 514, H04N 974, H04N 5268

Patent

active

051268450

ABSTRACT:
A pipeline bus having a plurality of slots in a backplane for receiving functional modules. A bus line is connected between the slots. A register and a selector are provided between each two adjacent slots. An image signal and a sync signal are transmitted from upper to lower slots in synchronism with the clock signal. The selectors output a signal either from the register or from the associated functional module to the register which is downstream.

REFERENCES:
patent: 4218709 (1980-08-01), Baxter et al.
patent: 4689823 (1987-08-01), Wojcik et al.
patent: 4800430 (1989-01-01), Murakami et al.
Kazumasa Enami, "Real-Time Video Signal Processor", SMPTE Journal, Dec. 1987, pp. 1158-1165.

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