Reduced gate error detection and correction circuit

Details Reduced gate error detection and correction circuit Reduced gate error detection and correction circuit

1995-03-31

1998-06-30

Baker, Stephen M.

Excavating

H03M 1300

Patent

active

057744815

ABSTRACT:
Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit position. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.

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