Interpolation circuit for interpolating error data block generat

Details Interpolation circuit for interpolating error data block generat Interpolation circuit for interpolating error data block generat

1996-03-20

1998-06-30

Elmore, Reba I.

Excavating

364723, G06F 1100, G06F 738

Patent

active

057744785

ABSTRACT:
An interpolation circuit and a recording and/or reproducing apparatus including an interpolation circuit are disclosed. The interpolating circuit calculates an average value of data positioned upstream and downstream of a defective data portion generated in a data string by an FIR filter having pre-set coefficient values, and calculates interpolated data from the average value. The Interpolation circuit also calculates an average value of data containing the defective data portion using the FIR filter and calculates the difference from the interpolated data for estimating the arraying pattern of the defective data portion. The interpolation circuit then determines an optimum array in the estimated arraying pattern and substitutes the optimum array for the defective data for repairing the defective data.

REFERENCES:
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patent: 4716565 (1987-12-01), Suma
patent: 5243428 (1993-09-01), Challapali et al.
patent: 5463714 (1995-10-01), Han
Japanese Patent Abstract, Publ. No. 1-55788, Tsukuru Hougiyoku, Data Interpolating Device For Digital Signal, Mar. 2, 1989.
Japanese Patent Abstract, Publ. No. 3-248376, Kiyotaka Nagai, Voice Band Division Decoder, Nov. 6, 1991.

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