Semiconductor memory device capable of realizing stable test mod

Details Semiconductor memory device capable of realizing stable test mod Semiconductor memory device capable of realizing stable test mod

1997-05-30

1998-06-30

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057744726

ABSTRACT:
In a semiconductor memory device, in a normal operation, data is written to selected four memory cells in accordance with external write data DQ0 to DQ3 applied to four data input/output terminals. In test mode, same data is commonly written to the selected four memory cells in accordance with write data DQ applied to one data input/output terminal. In the test mode operation, signal transmission between the remaining three data input/output terminals and the corresponding input buffer circuits is cut off by a CMOS logic gate provided therebetween and controlled in accordance with a test mode designating signal /TE.

REFERENCES:
patent: 5313424 (1994-05-01), Adams et al.
patent: 5467468 (1995-11-01), Koshikawa

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