Method of forming a stacked capacitor with an "I" shaped storage

Details Method of forming a stacked capacitor with an "I" shaped storage Method of forming a stacked capacitor with an "I" shaped storage

1995-01-20

1996-07-09

Tsai, H. Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

055344577

ABSTRACT:
A DRAM having a high capacitance stacked capacitor is fabricated by forming gate structures in the device areas and lines over field oxide areas on a substrate. A first insulating layer is formed and patterned to leave the source/drain structures open in the device areas where electrical contact is desired to the stacked capacitors. A bottom electrode of the capacitor is now formed by depositing and patterning a second polysilicon layer and a second insulating layer. Next the second polysilicon layer is laterally etched so that portions of the second polysilicon layer are etched out underneath from the second insulating layer. A third polysilicon layer is formed on the vertical sidewalls of the second polysilicon layer. A capacitor dielectric layer is deposited over the substrate surface and patterned so that portions remain covering the second and third polysilicon layers. A top electrode is formed over the capacitor dielectric layer.

REFERENCES:
patent: 5126916 (1992-06-01), Tseng
patent: 5155657 (1992-10-01), Oehrlein et al.
patent: 5192702 (1993-03-01), Tseng
patent: 5422295 (1995-06-01), Choi et al.
patent: 5441908 (1995-08-01), Lee et al.
patent: 5496758 (1996-03-01), Ema

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