Method for protecting a stacked gate edge in a semiconductor dev

Details Method for protecting a stacked gate edge in a semiconductor dev Method for protecting a stacked gate edge in a semiconductor dev

1995-05-02

1996-07-09

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 44, H01L 218247

Patent

active

055344550

ABSTRACT:
A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

REFERENCES:
patent: 5019527 (1991-05-01), Ohshima et al.
patent: 5120671 (1992-06-01), Tang et al.
patent: 5149665 (1992-09-01), Lee

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