Method and apparatus for generating instruction/data streams emp

Details Method and apparatus for generating instruction/data streams emp Method and apparatus for generating instruction/data streams emp

1996-04-01

1998-06-30

Gordon, Paul P.

Boots, shoes, and leggings

364488, 364490, 364578, 364184, 371 27, G06F 1560, G05B 1942

Patent

active

057743584

ABSTRACT:
A system (200) for generating an instruction/data stream (214) used to verify a hardware implementation of an integrated circuit design with respect to a higher level implementation. Upon execution, the instruction/data stream (214) causes boundary conditions, system events, interrupts, and exceptions of interest to be verified within the hardware implementation. In constructing the instruction/data stream (214), the system (200) receives (102) a plurality of templates (216) that describe partial behaviors of the integrated circuit design corresponding particular instructions. The system (200) then receives (104) a plurality of register models describe an operation of registers within the integrated circuit design. The system (200) then receives (106) a plurality of exception events that correspond to a potentially problematic operation of the hardware implementation. The system (200) then processes the plurality of templates, the plurality of register models, and the plurality of exception events to produce the instruction/data stream (214). The system (200) may also receive system element behavior (306) and process the system element behavior to validate operations of the hardware implementation for corresponding system elements.

REFERENCES:
patent: 5089973 (1992-02-01), Furtek
patent: 5422833 (1995-06-01), Kelem et al.
patent: 5455938 (1995-10-01), Ahmed
patent: 5497334 (1996-03-01), Russell et al.
patent: 5572437 (1996-11-01), Rostoker et al.

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