Controller for supplying multiplexed or non-multiplexed address

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395775, 395284, 395833, 39542101, 39542102, 395412, 364DIG1, G06F 1204

Patent

active

057548862

ABSTRACT:
A dynamic random access memory (RAM) addressing controller comprises a plurality of connectors connectible with a plurality of memory boards which use different addressing arrangements. A timing generator for generating a timing signal is provided for multiplexing address signals applied to a dynamic RAM storage. The controller also includes an input unit for applying an address signal of predetermined width, an address selector for mutliplexing a part of the address signal supplied from the input unit in accordance with the timing signal, a branching unit for supplying another part of the address signal of predetermined width from the input unit to a corresponding portion of each of the connectors respectively, and another branching unit for branching the address signal of the multiplexed part from the address selector in such a way as to be applied to a corresponding portion of each of the connectors. Memory boards carrying highly-integrated memory devices are replaceable in memory board slots.

REFERENCES:
patent: 4633392 (1986-12-01), Vincent et al.
patent: 4882727 (1989-11-01), Williams et al.
patent: 5097437 (1992-03-01), Larson

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