Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1990-04-24

1992-01-28

James, Andrew J.

357 2311, 357 51, 357 55, H01L 2968, H01L 2906, H01L 2702

Patent

active

050847465

ABSTRACT:
A semiconductor memory device having a folded bit line structure (16a, 16b), in which a field oxide film (2) is formed on both sides of a channel region (11) of a transfer gate, a groove isolation region 12 for defining a memory cell region is formed to surround the field oxide film 2, and the side walls of the groove isolation region 12 include a memory cell utilized as a capacitor for storing charges as information.

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patent: 4197554 (1980-04-01), Meusburger
patent: 4476547 (1984-10-01), Miyasaka
patent: 4493056 (1985-01-01), Mao
patent: 4717942 (1988-01-01), Nakamura et al.
patent: 4763178 (1988-08-01), Sakui et al.
"A New Memory Cell Layout Method for High Density Drams" IECE Japan, 1986 National Conference, Lecture No. 499.
"A 1Mb DRAM with a Folded Capacitor Cell Structure", Fumio Horiguchi et al., ISSCC85 Digest of Technical Papers, Feb. 1985, pp. 244-245.
1 Mb DRAM with a Folded Capacitor Cell Structure, IEEE International Solid-State Circuits Conference, Feb. 1985, pp. 244, 245, 355.

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