Method for forming a buried contact

Fishing – trapping – and vermin destroying

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Details

437 31, 437162, H01L 21283, H01L 21225

Patent

active

051262851

ABSTRACT:
A buried contact in a semiconductor device is formed by forming an oxide layer on a surface of a semiconductor substrate. A heavily-doped polysilicon layer is formed over the oxide layer and selectively etched to leave a first portion of the polysilicon layer over the surface and remove a second portion of the polysilicon layer from over the surface. The remaining first portion of polysilicon has a vertical surface which is over the surface of the substrate. After this step there is oxide between the first portion of the polysilicon layer and the substrate. An isotropic etch is performed which removes a portion of the oxide between the first portion of the polysilicon layer and the substrate to leave a void between the first portion of the polysilicon layer and the surface of the substrate from the vertical surface of the first portion of the polysilicon to a predetermined distance from the vertical surface of the first portion of the polysilicon layer. A polysilicon layer is then deposited which fills the void with polysilicon. The polysilicon which is not filling the void is removed. An implant is then performed using the first portion of the polysilicon layer as a mask to form a first doped region in the substrate adjacent to the vertical surface of the first portion of the polysilicon layer. Because the polysilicon layer was doped, dopant from the first portion of the polysilicon layer migrates down through the polysilicon filling the void to form a second doped region in the substrate under the first portion of the polysilicon layer which merges with the first doped region in the substrate. This has the effect making electrical contact between the first portion of the polysilicon layer and the first doped region in the substrate and thus achieving a desired buried contact.

REFERENCES:
patent: 4240196 (1980-12-01), Jacobs
patent: 4374700 (1983-02-01), Scott
patent: 4397076 (1983-08-01), Honnigford
patent: 4483726 (1984-11-01), Isaac
patent: 4531282 (1985-07-01), Sakai
patent: 4795719 (1989-01-01), Eitan
patent: 4824794 (1989-04-01), Tabata
patent: 4830972 (1989-05-01), Hamasaki
patent: 4892837 (1990-01-01), Kudo
patent: 4966864 (1990-10-01), Pfiester
Ghandhi, S. K., VLSI Fabrication Principles, Silicon & Golcium Arsenide, John Wiley & Sons, (1983), p. 373.

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