Switch circuit comprised of logically split switches for paralle

Details Switch circuit comprised of logically split switches for paralle Switch circuit comprised of logically split switches for paralle

1993-03-19

1998-05-19

Bowler, Alyssa H.

395312, 39580011, 39520079, G06F 15173, G06F 1300

Patent

active

057547920

ABSTRACT:
A parallel processor system including a plurality of processors. When packets of same destination PE number are inputted from different ports, the destination PE number is added with ID numbers of leading ports of split crossbar switches to which the different input ports belong, respectively, by using respective addition circuits, to thereby determine a transfer destination output port for the packets. A plurality of the split crossbar switches having different numbers of input/output ports are realized by partitioning a crossbar switch. By means of an input port select circuit provided in association with each of the output ports, an output request for the packet from the input port belonging to the split crossbar switch to which the associated output port belongs is accepted, while output requests for the packets from the input ports belonging to the other split crossbar switches are inhibited from being accepted, whereby transfer of broadcast packets are inhibited between the split crossbar switches belonging to a physically same crossbar switch. Such situation can be evaded in which same broadcast packets arrive at one and the same processor a number of times.

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IEEE Journal on Selected Areas in Communications, "A Reconfigurable ATM Switch for Fault Tolerance and Traffic Balancing", Shih-Chian Yang, et al., vol. 9, No. 8, Oct. 1991.

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