Multi-port semiconductor memory device with reduced coupling noi

Details Multi-port semiconductor memory device with reduced coupling noi Multi-port semiconductor memory device with reduced coupling noi

1996-05-20

1998-06-30

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257775, 257907, 365214, 36523005, H01L 2941

Patent

active

057738920

ABSTRACT:
A semiconductor memory device has two complementary pairs of bit lines coupled to the same memory cells. According to a first aspect of the invention, the bit lines in one complementary pair cross over, so that each bit line in the first pair runs adjacent to one bit line in the second pair for one part of its length, and adjacent to the other bit line in the second pair for another part of its length. Coupling noise is thereby neutralized. Data-inverting circuitry is provided to compensate for the inversion of data that results from the cross-over of the bit lines. According to a second aspect of the invention, the two complementary pairs of bit lines are placed in separate interconnecting layers, to reduce coupling noise by reducing the capacitive coupling between the bit lines.

REFERENCES:
patent: 4626889 (1986-12-01), Yamamoto
patent: 5170243 (1992-12-01), Dhong
patent: 5471093 (1995-11-01), Cheung
patent: 5585664 (1996-12-01), Ito
patent: 5594279 (1997-01-01), Itou
patent: 5602772 (1997-02-01), Nakano
Sugano, CMOS VLSI Design, Baifukan, Apr. 25, 1989, p. 231.

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