Semiconductor device having dummy wiring conductors for suppress

Details Semiconductor device having dummy wiring conductors for suppress Semiconductor device having dummy wiring conductors for suppress

1996-11-15

1998-06-30

Wallace, Valencia Martin

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257210, 257324, 257773, H01L 2710

Patent

active

057738572

ABSTRACT:
In a semiconductor device having a repetitive pattern area in which a unitary wiring pattern is repeatedly arranged and covered with a multilayer insulator film composed of a silicon oxide film and a TEOSBPSG film, dummy conductors formed of the same layer as that of conductors of the wiring pattern are formed in an area adjacent to an edge zone of the repetitive pattern area. Thus, the outermost conductor positioned at the edge of the repetitive pattern area is no longer the outermost patterned conductor in an extended repetitive pattern area including the dummy conductors. Thus, the stress which acts on the outermost conductor of the repetitive pattern area because of the shrinkage of the silicon oxide film caused for the difference in thermal shrinkage coefficient between the silicon oxide film and the TEOSBPSG film, is relaxed, so that the shifting of the outermost conductor is prevented, and therefore, a short-circuiting caused by shifting of the outermost conductor is also prevented.

REFERENCES:
patent: 4544238 (1985-10-01), Nickol
patent: 4916514 (1990-04-01), Nowak
patent: 5251168 (1993-10-01), Chung et al.
patent: 5441915 (1995-08-01), Lee

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