Excavating
Patent
1997-05-27
1998-05-19
Beausoliel, Jr., Robert W.
Excavating
G01R 3128
Patent
active
057545618
ABSTRACT:
An LSI equipped with an internal logic circuit which outputs a normal external output signal to the outside of the LSI during normal operation, and which outputs a test signal which is used for internal logic testing. An LSI is also equipped with an internal logic and unconnected/substandard-solder testing circuit which performs both internal logic testing and unconnected/substandard-solder testing. This internal logic and unconnected/substandard-solder testing circuit is equipped with an internal logic testing logic circuit into which the abovementioned test signals are input, an unconnected/substandard-solder testing logic circuit to which prescribed input and output terminals of the abovementioned LSI are connected, and one output logic circuit which controls the output of the above-mentioned internal logic testing logic circuit and the output of the abovementioned unconnected/substandard-solder testing logic circuit. Then, the abovementioned normal external output signal from the abovementioned internal logic circuit is supplied directly to the external output terminal of the LSI. Since this normal external output signal is output directly from the internal logic circuit to the external output terminal, without passing through gate circuits and the like, signal delays do not occur. Furthermore, it is possible to reduce the number of gate circuits because the circuits, which perform the internal logic testing and the unconnected/substandard-solder testing, have been made into a common circuit.
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Beausoliel, Jr. Robert W.
Elmore Stephen C.
Fujitsu Limited
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