Bit line discharge method for reading a multiple bits-per-cell f

Details Bit line discharge method for reading a multiple bits-per-cell f Bit line discharge method for reading a multiple bits-per-cell f

1997-06-27

1998-05-19

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

3651852, G11C 1134

Patent

active

057544751

ABSTRACT:
An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells are being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals. A reading circuit (26) is responsive to the strobe signals for comparing the memory core threshold voltage with each of the reference cell threshold voltages.

REFERENCES:
patent: 5029135 (1991-07-01), Okubo
patent: 5157626 (1992-10-01), Watanabe
patent: 5258958 (1993-11-01), Iwahashi et al.
patent: 5386132 (1995-01-01), Wong
patent: 5532962 (1996-07-01), Auclair et al.

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