Method and device for testing content addressable memory circuit

Details Method and device for testing content addressable memory circuit Method and device for testing content addressable memory circuit

1996-05-17

1998-12-08

Nguyen, Hoa T.

Excavating

371 271, 371 211, 371 2231, G11C 2900, G01R 3178

Patent

active

058480749

ABSTRACT:
Automatic generation of a test pattern for test data to test a content addressable memory for failure is disclosed. An inverter (INV1) inverts a scan signal (SODI) outputted from a scan path to apply the inverted scan signal to a 1-input of a selector (SEL1). A scan input (SIDI) is the inverted version of a scan output from a scan flip-flop (SFF-D12). To test a content addressable memory (100), a test signal (CAMTEST) is set to "1", thereby producing input signals (DI0, DI1, DI2) in such a looped manner as: (0, 0, 0).fwdarw.(1, 0, 0).fwdarw.(1, 1, 0).fwdarw.(1, 1, 1).fwdarw.(0, 1, 1).fwdarw.(0, 0, 1).fwdarw.(0, 0, 0).fwdarw. . . . .

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