Method and structure for controlling operation of a DRAM array

Details Method and structure for controlling operation of a DRAM array Method and structure for controlling operation of a DRAM array

1998-05-12

2000-06-20

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

3652335, G11C 800

Patent

active

060785470

ABSTRACT:
A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.

REFERENCES:
patent: 5615169 (1997-03-01), Leung
patent: 5708624 (1998-01-01), Leung
patent: 5778237 (1998-07-01), Yamanoto et al.
patent: 5829026 (1998-10-01), Leung et al.

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