Semiconductor memory device implementing multi-bank configuratio

Details Semiconductor memory device implementing multi-bank configuratio Semiconductor memory device implementing multi-bank configuratio

1998-12-03

2000-06-20

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365196, G11C 800

Patent

active

06078542&

ABSTRACT:
A memory cell array in a semiconductor memory device according to the present invention is divided into a plurality of banks along the row-direction. Each bank is further divided into a plurality of sub blocks along the column-direction. Sub blocks belonging to the same group, in other words, sub blocks arranged adjacent to each other along the row-direction share the same row address. An accessing operation to an addressed memory cell is performed on the basis of a sub block. The activation of a sub block is performed by a control circuit provided for each of the sub blocks based on a signal activated for each of the banks and the same group based on an address signal.

REFERENCES:
patent: 5831924 (1998-11-01), Nitta et al.
patent: 5867440 (1999-02-01), Hidaka
"A 32-Bank Gb Self-Strobing Synchronous DRAM with 1GByte/s Bandwidth", J. Yoo et al., IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1635-1643.
"A 1.6-GB/s Data-Rate 1-Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture", N. Sakashita et al., IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1645-1655 .

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