Consistency protocols for shared memory multiprocessors

Details Consistency protocols for shared memory multiprocessors Consistency protocols for shared memory multiprocessors

1993-02-26

1993-11-23

Bowler, Alyssa H.

Boots, shoes, and leggings

395725, 364DIG1, 36424341, 36424345, 36424344, 3642408, G06F 1200, G06F 1208, G06F 1314, G06F 1516

Patent

active

052652351

ABSTRACT:
A shared memory multiprocessor having a packet switched bus, together with write back caches for connecting individual processor to that bus, employs a consistency protocol that permits the caches to store multiple copies of read/write data at identical physical addresses for use as needed by the respective processors. The protocol causes the hardware to automatically and transparently maintain the consistency of this data. To that end, the caches detect when a datum becomes shared by monitoring the traffic on the bus, thereby enabling them to broadcast an updating write on the bus whenever their respective processors issue a write to a shared address. If desired, this protocol may be extended to include an advisory invalidate for reducing the amount of address sharing that occurs, thereby enhancing the efficiency of the protocol. The protocol maintains a consistent view of memory for the processors, while permitting I/O devices to have direct access to the memory system.

REFERENCES:
patent: 4843542 (1989-06-01), Dashiell et al.
patent: 5025365 (1991-06-01), Mathur et al.
David V. James edited by Dubois et al., "Cache and Interconnect Architectures in Multiprocessors, SCI (Scalable Coherent Interface) Cache Coherence," Kluwer Academic Publishers, 1990, pp. 189-208.
Andrew W. Wilson, Jr., "Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors," Computer Architecture Conference (IEEE/ACM), 1987, pp. 244-252.

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