Boots – shoes – and leggings
Patent
1990-07-02
1993-11-23
Coleman, Eric
Boots, shoes, and leggings
364260, 3642602, 3642651, 3642443, 364DIG1, G06F 1300
Patent
active
052652297
ABSTRACT:
An interleaved output queue is used as a high performance interface on a system bus for transferring information from a CPU to main memory. The queue is loaded on its input side with information that is bound for transmission from the CPU's cache to main memory. The queue itself is logically divided into those queue entry addresses which are either odd or even. On its output side, the queue is unloaded by dual sets of unload circuitry, each of which accesses the information stored in either the odd or even queue entry addresses. Other select circuitry will alternate the transmission of information out of the two sets of unload circuitry to main memory. Each set of unload circuitry receives error information back from main memory during the time that the other unload circuitry is issuing a transaction. As a result, each set of unload circuitry is thereby informed whether its own previous transaction was error free, in which case it will transmit the information contained in its next queue entry address when it next issues a transaction, or whether its previous transaction was not error free, in which case it will next have to resend the same information sent during the previous transaction. Consequently, transactions issued from the queue can proceed in an immediately successive sequence without waiting for the processing of error information from the immediately preceding transaction yet the queue can still recover form errors during high performance operation.
REFERENCES:
patent: 4451880 (1984-05-01), Johnson
patent: 4482956 (1984-11-01), Tallman
patent: 4558429 (1985-12-01), Barlow
patent: 4779234 (1988-10-01), Kaneko
patent: 4807111 (1989-02-01), Cohen
patent: 4894797 (1990-01-01), Walp
patent: 4949301 (1990-08-01), Joshi
Coleman Eric
Digital Equipment Corporation
Skladony William P.
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