Method and apparatus for error correction

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371 401, G06F 1110

Patent

active

048812323

ABSTRACT:
An error-correcting method and apparatus for a block of data provided with an error-correcting parity for error correction and an error-checking parity that can be used to generate a syndrome for error-checking, in which error correction is carried out by the use of the error-correcting parity and then an error check is carried out by the use of the error-checking parity thereby to increase the reliability of the error-checking data, wherein error information produced by the error-correction process using the error-correcting parity is utilized to correct the syndrome used in the error-checking process, so as to execute the respective operations in parallel and reduce the required data processing time or through-put.

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patent: 4750178 (1988-06-01), Sako et al.
patent: 4760576 (1988-07-01), Sako
patent: 4785451 (1988-11-01), Sako et al.
patent: 4788685 (1988-11-01), Sako et al.
patent: 4819236 (1989-04-01), Sako et al.

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