Digital signal delaying method and circuit

Details Digital signal delaying method and circuit Digital signal delaying method and circuit

1996-06-14

1998-05-19

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327265, 327263, H03K 5135

Patent

active

057540713

ABSTRACT:
A digital signal delay circuit includes a first pair of counters for setting a starting point of a digital output signal by counting an adjustably set number of clock pulses corresponding to an intended time delay from a starting point of a digital input signal. The circuit further includes a second pair of counters for setting an ending point of the digital output signal by counting an adjustably set number of clock pulses corresponding to an intended output pulse width from an ending point of the digital input signal. The state of the digital output signal is only determined by the state of the output signal of the last counter in the first pair of counters. The output signal from the last counter in the first pair of counters controls a count starting point of the first counter in the second pair of counters. The output signal from the second pair of counters controls an initializing point on which the state of the output signal from the last counter in the first pair of counters is inverted.

REFERENCES:
patent: 4795984 (1989-01-01), Janssen
patent: 5617452 (1997-04-01), Haulin et al.
patent: 5617458 (1997-04-01), Jones et al.
R. E. S. Abdel-Aal, "Synchronous counters provide programmable pulse delays", Electronics, vol. 52, No. 4, pp. 119-121, Feb. 15, 1979.

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