Method for forming a passivation layer with planarization

Details Method for forming a passivation layer with planarization Method for forming a passivation layer with planarization

1998-10-14

2000-06-20

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438734, 438742, 438754, H01L 2100

Patent

active

060777893

ABSTRACT:
A method for forming a passivation layer with improved planarity includes patterning a top interconnect metal layer through two steps of etching, in which the metal layer is formed over a substrate that has device elements already formed thereon. The first etching process is isotropic etching, which undercuts an etching mask layer. The upper sharp corners of the metal layer are removed. The second etching process in anisotropic etching to complete an opening that exposes the substrate. A PSG layer and a silicon nitride layer are sequentially formed to serve as a passivation layer. Since the aspect ratio is reduced due to undercutting, a void within the opening is avoided, and a crack in the passivation layer within the opening is also avoided.

REFERENCES:
patent: 4352724 (1982-10-01), Sugishima et al.
patent: 4986877 (1991-01-01), Tachi et al.

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