Single PAL circuit generating system clock and control signals t

Details Single PAL circuit generating system clock and control signals t Single PAL circuit generating system clock and control signals t

1993-08-16

1995-06-20

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 364270, 3642701, 395775, G06F 100, G06F 104, G06F 110

Patent

active

054267722

ABSTRACT:
The invention is for improving the performance of a microprocessor system by reducing the skew between the system clock and critical control signals. Reduction in this skew reduces or eliminates the need for waitstates on data accesses to random access memory devices thereby improving system performance. A clock PAL is programmed to function as an asynchronous state machine to generate the clock signals and the memory device chip select. A clock source from an oscillator is input to the PAL. This clock source is buffered by the PAL and presented at the PAL outputs as the system clock. The memory device chip select is also generated inside this PAL using the source clock and other signals generated inside the PAL.

REFERENCES:
patent: 4851995 (1989-07-01), Hsu et al.
patent: 4926066 (1990-05-01), Maine et al.
patent: 4989175 (1991-02-01), Boris et al.
patent: 5036230 (1991-07-01), Bazes
patent: 5097437 (1992-03-01), Larson

Affiliated with

Also associated with

Rating

Single PAL circuit generating system clock and control signals t does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single PAL circuit generating system clock and control signals t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single PAL circuit generating system clock and control signals t will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1851177