Boots – shoes – and leggings
Patent
1993-09-27
1995-06-20
Envall, Jr., Roy N.
Boots, shoes, and leggings
364761, 364766, 395250, 395400, 395800, G06F 752
Patent
active
054266009
ABSTRACT:
An arithmetic operation execution unit includes a plurality of 2N bit data registers and an arithmetic logic unit (ALU). The execution unit is coupled to data busses each having a data path width of N bits for transferring data to and from the data registers. An XOR gate and inverter gate are provided for computing a quotient bit QB and a next ALU operation command bit QOP. A bit processing unit (BPU) shifts the QB bit generated during the previous instruction cycle into an output register during each instruction cycle. The execution unit responds to three predefined division instructions by configuring the ALU, BPU and XOR gate to perform three distinct functions. A first instruction performed for each division computation computes initial QB and QOP values. A second instruction is executed multiple times. Each execution of the second instruction computes one quotient bit QB, shifts a quotient bit computed in the prior instruction cycle into the least significant bit of a destination register, and also computes a QOP value that determines the next ALU operation to be performed. A final instruction shifts the last computed quotient bit into the destination register and also adds the divisor to the dividend register if the QOP value computed in the prior instruction cycle has a predefined value. For double precision division computations, each of the first and second instructions is followed by a "rotate with carry" instruction that shifts one bit of the dividend's lower 2N bits into a carry bit register, which is then shifted into the upper dividend by the next instruction executed.
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Kiuchi Atsushi
Nakagawa Tetsuya
Envall Jr. Roy N.
Hitachi America Ltd.
Moise Emmanuel
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