Hardware implemented multiplier for performing multiplication of

Details Hardware implemented multiplier for performing multiplication of Hardware implemented multiplier for performing multiplication of

1993-05-19

1995-06-20

Mai, Tan V.

Boots, shoes, and leggings

G06F 752

Patent

active

054265991

ABSTRACT:
The multiplier includes a register circuit for holding a multiplicand X, a multiplier register circuit for holding a multiplier Y, a second order Booth decoder circuit for decoding prescribed less significant bits of the multiplier Y according to the second Booth algorithm, and a third order Booth decode circuit for decoding more significant bits of the multiplier Y according to the third Booth algorithm. A tripled of the multiplicand X is produced in a 3X producing circuit in parallel with a multiplication operation utilizing the second Booth algorithm in an adder array. The output of adder array together with the output of 3X producing circuit is applied to an adder array for executing a multiplication operation according to the third order Booth algorithm. Production of an odd number multiple data of the multiplicand necessary for the third order Booth algorithm is executed in parallel with the multiplication operation according to the second order Booth algorithm, and therefore time required for producing the triple can apparently be eliminated. Thus, a multiplier capable of executing multiplication at a high speed in a hardware manner is provided.

REFERENCES:
patent: 4965762 (1990-10-01), Williams
patent: 5070471 (1991-12-01), Dao-Trong et al.
patent: 5150322 (1992-09-01), Smith et al.
"A Signed Binary Multiplication Technique" by A. D. Booth, 1951, Oxford Univ. Press.

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