Arithmetic logic unit controller

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G06F 750

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active

043193358

ABSTRACT:
A high speed parallel digital adder includes a control circuit which is the subject of this invention. The control circuit is a single integrated circuit having: add/subtract select logic for selecting the addition and subtraction functions of the adder; a one's complement carry look ahead logic unit for generating carry look ahead signals; and a logic unit for generating the sign of the resultant of the two operands, a complement data output, the underflow, and the overflow.

REFERENCES:
patent: 3697735 (1972-10-01), Hanson
patent: 3947671 (1976-03-01), Geng et al.
patent: 3970833 (1976-07-01), Gehweiler et al.
patent: 3993891 (1976-11-01), Beck et al.

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