Method of making transistor devices in an SRAM cell

Details Method of making transistor devices in an SRAM cell Method of making transistor devices in an SRAM cell

1993-11-30

1995-06-20

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 148DIG163, H01L 218229

Patent

active

054260655

ABSTRACT:
An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.

REFERENCES:
patent: 3731161 (1973-05-01), Yamamoto
patent: 4177096 (1979-04-01), Okumura et al.
patent: 4471373 (1984-09-01), Shimizu
patent: 4806500 (1989-02-01), Scheibe

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