Shared floating-point registers and register port-pairing in a d

Details Shared floating-point registers and register port-pairing in a d Shared floating-point registers and register port-pairing in a d

1995-11-29

1997-11-04

Bowler, Alyssa H.

395566, 395500, 395568, 395587, G06F 930

Patent

active

056850093

ABSTRACT:
A dual-instruction-set central processing unit (CPU) is capable of executing floating point instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Floating point data is transferred from a CISC program to a RISC program running on the CPU by using shared floating point registers. The architecturally-defined floating point registers in the CISC instruction set are merged or folded into some of the architecturally-defined floating point registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the floating-point exception-mask and flags registers defined by each architecture are merged together so that CISC instructions and RISC instructions implicitly update the same merged flags register when executing floating point instructions. The RISC and CISC registers are folded together so that the CISC flags and RISC flags with the same function are merged to the same register bit. The floating-point data registers are also merged together, allowing a CISC program to pass floating-point data to a RISC program merely by writing one of its floating-point data registers, switching control to the RISC program, and the RISC program reading one of its floating-point data registers that is merged with and corresponds to the CISC floating-point data register that was written to by the CISC program. An extended-precision CISC data format is supported by pairing two of the RISC-size floating-point data registers.

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