Patent
1995-06-01
1997-11-04
Beausoliel, Jr., Robert W.
39518321, 39518504, G06F 1100
Patent
active
056849478
ABSTRACT:
A performance evaluation for a parallel computer which carries out parallel processing in multiple processor by means of transmitting or receiving a message among the processors. Execution starting time, standby starting time for waiting reception of the message, message number on reception of the message, processor number of the processor, the message and time when the message is received, message number on transmitting of the message and time when the message execution ending time are memorized. A maximum delay path is determined for the execution which has lastly been ended, the standby starting time for waiting reception of the message in the last ending processor, the message number of the last ending processor, the transmitting processor number and the message transmitting processor corresponding to the transmitting processor number. Processing is repeatedly carried out from the last ending processor to starting processor where execution of the parallel processing is started. Thus, the maximum delay path is identified.
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Beausoliel, Jr. Robert W.
Fujitsu Limited
Palys Joseph E.
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