Boots – shoes – and leggings
Patent
1995-02-17
1997-11-04
Louis-Jacques, Jacques
Boots, shoes, and leggings
364488, 364490, 364491, 395921, 395919, G06F 1500, G06F 1750
Patent
active
056847092
DESCRIPTION:
BRIEF SUMMARY
This application is 371 of PCT/DE93/00701 filed on Aug. 6, 1993.
BACKGROUND OF THE INVENTION
The specification of complex integrated circuits can be performed on different planes of abstraction. A hardware description language, for example VHDL, can be used for this purpose. A validation of the specification by commercially available simulators is possible, with the result that it can be checked whether the specification also fulfills the design task.
When the specification has been drawn up, a synthesis program is used to transfer the specification to a lower plane of abstraction and, for example, circuits are generated on a register-transfer plane using a high-level synthesis program. This method is described, for example, in M. McFarland, A. Parker and R. Camposano, "The high level synthesis of digital systems", in Proceedings of the IEEE, Vol. 78, pages 301 to 318, February 1990. Conventional design automation systems thus support the further design path. If the synthesized circuits are not purely combinatorial, they work in a completely synchronous fashion with a global clock signal and are constructed from a data path having a controller. The circuit is always a Moore automaton which is transferred to its next state by the rising clock pulse edge in each case.
The utility of the high-level synthesis depends on an affirmative answer to the two following questions: the specification fulfills the design task? implementation as possible?
However, these two aims run counter with respect to the specification of the temporal circuit behavior: the optimization potential of the synthesis increases drastically if it is permissible to vary the temporal interface behavior of the Moore automaton generated; however, an algorithmic specification which permits this cannot generally be readily validated by simulation, because conventional simulators do not know temporal degrees of freedom. Consequently, it can only be determined by simulation of the synthesis result whether the circuit communicates correctly with its environment, although this is already to be ensured before synthesis by the specification.
SUMMARY OF THE INVENTION
The object of the invention is to specify a method for generating a circuit arrangement comprising circuits with the aid of a computer, in which the specification of the temporal circuit behavior is such that the two questions mentioned above can be answered in the affirmative. This object is achieved by means of the method of the present invention for designing a circuit arrangement, having circuits, with the aid of a computer. The circuit arrangement is specified on an algorithmic plane and this specification is translated by a synthesis program into circuits on the register-transfer plane. In the specification on an algorithmic plane in accordance with the time response of a circuit to be selected, it is the case that in the specification, in clock cycles in each instance, between the reading of the input signals and the writing of the output signals either a fixed t.sub.v is prescribed in the specification and a constant time t.sub.i which is to be established by the synthesis program is used, or initially indeterminate time .infin. is used which is not to be established until after selection of the circuit.
The high-level synthesis program usually converts an algorithmic circuit specification firstly into an internal flow graph representation. Consequently, the aim below is to describe the invention with the aid of such a representation (cf. R. Camposano and R. Tabet "Design representation for the synthesis of behavioral VHDL models" in CHDL, Proc. of the Ninth IFIP Symposium 1989). The flow graph is a directional graph whose nodes are the operations in the algorithmic specification.
The edges are defined by the sequential processing sequence of the operations. The time specification of read and write signals (input signals, output signals of the circuits to be selected) is expressed in the flow graph by means of so-called time nodes which are provided with the following attribut
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Louis-Jacques Jacques
Siemens Aktiengesellschaft
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