Multiphase series-parallel-series charge-coupled device register

Details Multiphase series-parallel-series charge-coupled device register Multiphase series-parallel-series charge-coupled device register

1975-06-30

1977-05-17

Curtis, Marshall M.

Communications: electrical

Digital comparator systems

357 24, G11C 1144

Patent

active

040245144

ABSTRACT:
The invention comprises a charge-coupled device shift register for storing and transferring bits of information in the form of small packets of charge. The apparatus utilizes multiphase clocking to allow for high density storage within the register which is comprised of three sections: serial input section, central storage section and serial output section. The serial input section receives charge packets synchronously from an injector circuit and is driven by two phase clocking. The central section forms the heart of the storage and transfer mechanism and is driven by multiphase clocking. The serial output section, also driven by two-phase clocking, synchronously emits charge packets which are sensed and amplified by a sense amplifier circuit.
The input and output sections each contain (almost) twice the number of cell sites as the number of bits which are transferred in parallel through the central section. However, these sections store data bits in only every other cell site. Data bits are transferred into and out of the central section in one parallel step, thereby minimizing the clocking requirements of the register and allowing for high density CCD chips containing such registers.

REFERENCES:
patent: 3913077 (1975-10-01), Erb
patent: 3914748 (1975-10-01), Barton et al.
B545,945, Jan. 1976, Chan, 340/173 CA.

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