Semiconductor device having a PN junction formed on an insulator

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357 34, 357 49, 357 56, H01L 2972, H01L 2712, H01L 2906, H01L 2904

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048190551

ABSTRACT:
The invention deals with a semiconductor device which comprises a semiconductor substrate of a first conductivity type, a semiconductor region formed on said substrate, and a first insulation film provided between said semiconductor region and said semiconductor substrate, wherein said semiconductor substrate is isolated by said insulation film from a polycrystalline silicon layer formed in the periphery of said semiconductor region thereby to reduce the parasitic capacitance, and wherein said insulation film is stretched and arranged on the lower side of said semiconductor region.

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patent: 4303933 (1981-12-01), Horng et al.
patent: 4433470 (1984-02-01), Kameyama et al.
patent: 4512075 (1985-04-01), Uora
patent: 4609407 (1986-09-01), Masao et al.
S. K. Wiedmann, "Status and Trends of I.sup.2 L/MTL Technology", IEDM 83 (Dec. 1983) pp. 47-50.
F. Barson, "Improved NPN Process and Structure", IBM Technical Disclosure Bulletin, vol. 23, No. 9, (Feb. 1981) pp. 4166-4167.
A. S. Grove, Physics and Technology of Semiconductor Devices, John Wiley & Sons, New York (1967) pp. 78-83.

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