Boots – shoes – and leggings
Patent
1993-12-07
1995-09-19
Bowler, Alyssa H.
Boots, shoes, and leggings
395800, 395775, 364262, 3642628, 364DIG1, G06F 926, G06F 906
Patent
active
054524253
ABSTRACT:
A constant generator is described which provides a sequence of digital constants in a synchronous vector processor. The constant generator includes a constant loop memory for storing data words organized into a plurality of data constant patterns and an end of loop bit, a constant loop counter for supplying sequential addresses to the constant loop memory, and a constant loop counter controller for loading the counter with one of a set of predetermined starting addresses associated with a desired constant pattern stored in the constant loop memory. Additionally, a method of supplying a sequence of digital constants in said constant generator is disclosed and includes the steps of storing a plurality of data words in a plurality of constant patterns, where each constant pattern includes an end of loop bit, supplying an address to the constant loop memory and supplying sequential addresses to the constant loop memory.
REFERENCES:
patent: 3646522 (1972-02-01), Furman et al.
patent: 3689895 (1972-09-01), Kitamura
patent: 3736567 (1973-05-01), Lotus et al.
patent: 3924109 (1975-12-01), Jhu et al.
patent: 3979728 (1976-09-01), Reddaway
patent: 4159520 (1979-06-01), Prioste
patent: 4173041 (1979-10-01), Dvorak et al.
patent: 4249248 (1981-02-01), Yomogida et al.
patent: 4438492 (1984-03-01), Harmon, Jr. et al.
patent: 4462074 (1984-07-01), Linde
patent: 4727483 (1988-02-01), Saxe
patent: 4739474 (1988-04-01), Holsztynski et al.
patent: 4792892 (1988-12-01), Mary et al.
patent: 4821176 (1986-04-01), Ward et al.
patent: 4858115 (1989-08-01), Rusterholz et al.
patent: 4858178 (1989-08-01), Breuningan
patent: 5056004 (1991-10-01), Ohde et al.
patent: 5081573 (1992-01-01), Hall et al.
patent: 5128857 (1992-07-01), Okada et al.
patent: 5210836 (1993-05-01), Childers et al.
Fisher, Allan L., et al., Architecture of a VLSI SIMD Processing Element, IEEE International Conference on Circuits and Design, 1987, pp. 324-327.
van Rowermud, A. H. M., et al., A General-Purpose Programmable Video Signal Processor, ICCE 1989 VSP/Phillips.
Chin, D., et al., The Princeton Engine: A Real-Time Video System Simulator, IEEE Transactions on Consumer Electronics, vol. 34, No. 2, May 1988, pp. 285-297.
Nakagawa, Shin-ichi, et al., A 50 ns Video Signal Processor, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, vol. XXXII, 1989, pp. 168-169, 328.
Kikuchi, Kouichi, et al., A Single-Chip 16-Bit 25 ns Relatime Video/Image Signal Processor, IEEE ISSCC Digest of Technical Papers, vol. XXXII, 1989, pp. 170-171, 329.
Wilson, Stephens S., The Pixie-5000-A Systolic Array Processor, IEEE 1985, pp. 477-483.
Davis, Ronald, et al., Systolic Array Chip Matches The Pace Of High-Speed Processing, Electronic Design, Oct. 21, 1984, pp. 207-218.
Hannaway, Wyndham, et al., Handling Real-Time Images Comes Naturally to Systolic Array Chip, Electronic Design, Nov. 15, 1984, pp. 289-300.
Smith, Jr., Winthrop W. et al., Systolic Array Chip Recognizes Visual Patterns Quicker Than A Wink, Electronic Design, Nov. 29, 1984, pp. 257-266.
Wallis, Lyle, Associative Memory Calls On The Talents Of Systolic Array Chip, Electronic Design, Dec. 13, 1984, pp. 217-226.
Fisher, Allan L., et al, Real-Time Image Processing On Scan Line Array Processors, IEEE 1985, pp. 484-489.
Fisher, Allan L., Scan Line Array Processor For Image Computation IEEE 13th Annual International Symposium on Compu. Arch., Compu. Arch. News, vol. 14, No. 2, Jun. 1986, pp. 338-345.
Waltz, David L. Applications of the Connection Machine, IEEE Computer Magazine, Jan. 1987, pp. 85-97.
Webber, Donald M. et al., Circuit Simulation on the Connection Machine, 24th ACM/IEEE Design Automation Conference, 1987, pp. 108-113.
Hills, W. Daniel, text book excerpt, The Connection Machine, The MIT Press series in artificial intelligence-Thesis (PH.D.)-MIT, 1985, pp. 18-28.
Fountain, T. J., text book, Integrated Technology for Parallel Image Processing, "Plans for the CLIP7 Chip.", pp. 199-214, Chapter 13.
Gharachorloo, Nader, et al., A Systolic VLSI Graphics Engine For Real-Time Raster Image Generation, 1985 Chapel Hill Conference on VLSI, pp. 285-305.
Childers Jim
Miyaguchi Hiroshi
Reinecke Peter
An Meng-Ai T.
Bowler Alyssa H.
Donaldson Richard L.
Kesterson James C.
Marshall, Jr. Robert D.
LandOfFree
Sequential constant generator system for indicating the last dat does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sequential constant generator system for indicating the last dat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sequential constant generator system for indicating the last dat will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1835434