System and method for designing a finite state machine to reduce

Details System and method for designing a finite state machine to reduce System and method for designing a finite state machine to reduce

1994-08-24

1995-09-19

Trammell, James P.

Boots, shoes, and leggings

364489, 364490, 364491, G05B 19418

Patent

active

054522153

ABSTRACT:
Accordingly, a digital logic circuit in the form of a finite state machine (FSM) is implemented in a semiconductor structure such as complementary metal oxide silicon (CMOS) with reduced power dissipation by determining transition probabilities for transitions between states in the FSM, producing a constraint matrix to identify constraints to producing a minimum area implementation consistent with minimum power dissipation, constructing one or more state chains having transitions with highest probability and implementing each of these state chains in order of probability to achieve the implementation of the FSM having minimum power dissipation.

REFERENCES:
patent: 4580228 (1986-04-01), Noto
patent: 5119314 (1992-06-01), Hotta et al.
patent: 5140402 (1992-08-01), Murakata
patent: 5212653 (1993-05-01), Tanaka
patent: 5225991 (1993-07-01), Dougherty
patent: 5267175 (1993-11-01), Hooper
patent: 5283753 (1994-02-01), Schucker et al.
patent: 5311079 (1994-05-01), Ditlow et al.
S. Devadas and A. R. Newton, "Exact Algorithms for Output Encoding, State Assignment and Four-Level Boolean Minimization," IEEE Transactions on Computer-Aided Design Integr. Circuits Syst., vol. 10, No. 1, pp. 13-27, Jan. 1991.
G. De Micheli, R. Brayton, and A. L. Sangiovanni-Vincentelli, "Optimal State Assignment for Finite State Machines," IEEE Transactions on Computer-Aided Design, vol. CAD-4, No. 3 pp. 269-284, Jul. 1985.
G. De Micheli, "Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-level Logic Macros," IEEE Transactions on Computer-Aided Design, vol. CAD-5, No. 4, pp. 597-616, Oct. 1986.
R. Amann and U. Baitinger, "Optimal State Chains and State Codes in Finite State Machines," IEEE Transactions on Computer-Aided Design, vol. 8, No. 2, Feb. 1989.
S. Yang and M. Ciesielski, "On the Relationship Between Input Encoding and Logic Minimization," 23rd Annual Hawaii International Conference in System Sciences, vol. 1, pp. 377-386, 1990.
S. Devadas, H-K. T. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli, "Mustang: State Assignment of Finite State Machines for Optimal Multi-Level Logic Implementations",: IEEE Transactions on CAD, vol. 7, Dec. 1988.
B. Lin and A. R. Newton, "Synthesis of Multiple Level Logic from Symbolic High-Level Description Languages," VLSI, 1989.
A. Shen, A. Ghosh, S. Devadas, K. Keutzer, "On Average Power Dissipation and Random Pattern Testability of CMOS Combinational Logic Networks," Proc. IEEE ICCAD, pp. 402-407, Nov. 1992.
X. Du, G. Hactel, P. Moceyunas, "MUSE: A Multilevel Symbolic Encoding Algorithm for State Assignment," Proceedings of the Twenty-Third Annual Hawaii International Conference on System Sciences, pp. 367-376, 1990.
K. Roy, S. Prasad, "Circuit Activity Based Logic Synthesis for Low Power Reliable Operations," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, No. 4, pp. 503-513, Dec. 1993.
K. Roy, S. Prasad, "SYCLOP: Synthesis of CMOS Logic for Low Power Applications",: IEEE International Conference on Computer Design, pp. 464-467, Oct. 1992.
J. Hennessy and D. Patterson. Computer Architecture, A Quantitative Approach. San Mateo, Calif.: Morgan Kaufmann Publishers, Inc., 1990.
R. Rudell and A. Sangiovanni-Vincentelli, "Espresso-MV: Algorithms for Multi-valued Logic Minimization," Proc. Custom Int. Circ. Conf., Portland, Oreg., May 1985.

Affiliated with

Also associated with

Rating

System and method for designing a finite state machine to reduce does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for designing a finite state machine to reduce, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for designing a finite state machine to reduce will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1833591