Method of forming raised source/drain regions in a integrated ci

Details Method of forming raised source/drain regions in a integrated ci Method of forming raised source/drain regions in a integrated ci

1995-06-07

1997-11-04

Niebling, John

Fishing, trapping, and vermin destroying

437 41, 437186, H01L 21265

Patent

active

056839243

ABSTRACT:
A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of field oxide regions are formed overlying a substrate electrically isolating a plurality of transistors encapsulated in a dielectric. LDD regions are formed in the substrate adjacent the transistors and the field oxide regions. Doped polysilicon raised source and drain regions are formed overlying the LDD regions and a tapered portion of the field oxide region and adjacent the transistor. These polysilicon raised source and drain regions will help to prevent any undesired amount of the substrate silicon from being consumed, reducing the possibility of junction leakage and punchthrough as well as providing a more planar surface for subsequent processing steps.

REFERENCES:
patent: 4450620 (1984-05-01), Fuls et al.
patent: 4775644 (1988-10-01), Szeto
patent: 4807013 (1989-02-01), Manocha
patent: 4841347 (1989-06-01), Hsu
patent: 4859620 (1989-08-01), Wei et al.
patent: 4868138 (1989-09-01), Chan et al.
patent: 4937643 (1990-06-01), Deslauriers et al.
patent: 4940509 (1990-07-01), Tso et al.
patent: 4948745 (1990-08-01), Pfiester et al.
patent: 5079180 (1992-01-01), Rodder et al.
patent: 5118639 (1992-06-01), Roth et al.
patent: 5141891 (1992-08-01), Arima et al.
patent: 5158903 (1992-10-01), Hori et al.
patent: 5182619 (1993-01-01), Pfiester
patent: 5192992 (1993-03-01), Kim et al.
patent: 5241193 (1993-08-01), Pfiester et al.
patent: 5242847 (1993-09-01), Ozturk et al.
patent: 5319232 (1994-06-01), Pfiester
patent: 5341016 (1994-08-01), Prall et al.
patent: 5365081 (1994-11-01), Yamazaki et al.
patent: 5496750 (1996-03-01), Moslehi
patent: 5504031 (1996-04-01), Hsu et al.
Rodder, et al., "Raised Source/Drain MOSFET with Dual Sidewall Spacers", IEEE Electron Device Letters 12 (1991) Mar., No. 3, New York.
Wong, et al., "Elevated Source/Drain Mosfet", 1984 International Electron Devices Meeting, Dec. 9-12, 1984, IEDM, pp. 634-637.
1046B Extended Abstracts/Spring Meeting 88-1 (1988), May 15-20, Princeton, NY, p. 301.
Queirolo, et al., "Dopant Activation, Carrier Mobility, and TEM Studies in Polycrystalline Silicon Films", J. Electrochem. So., V. 137, No. 3, Mar., 1990, pp. 967-970.
C.S. Pai, et al., "Chemical IVapor Deposition of Selective Epitaxial Silicon Layers", J. Electrochem. Soc., V. 137, No. 3, Mar., 1990, pp. 971-976.

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