Method of fabricating a self-aligned contact

Details Method of fabricating a self-aligned contact Method of fabricating a self-aligned contact

1996-10-04

1997-11-04

Quach, T. N.

Fishing, trapping, and vermin destroying

437193, 437195, 437200, 437978, 437984, H01L 21283, H01L 2131

Patent

active

056839227

ABSTRACT:
A method of forming a self-aligned contact for a transistor formed on a substrate. A self-aligned silicide layer is formed on the surface of a source/drain region of the transistor. A silicon oxide/silicon nitride layer is formed over the transistor. Then, a planarization process is performed to fill a trench between gates with, for example, borophosphosilicate glass. In particular, wet etching using a 20:1 buffered oxide etchant is performed to increase the selectivity of the silicon oxide/silicon nitride layer.

REFERENCES:
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5246882 (1993-09-01), Hartmann
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5436188 (1995-07-01), Chen
patent: 5478768 (1995-12-01), Iwasa

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