Barrier emitter transistor

Details Barrier emitter transistor Barrier emitter transistor

1984-04-16

1987-06-09

James, Andrew J.

357 16, 357 34, 357 88, 357 59, H01L 4902, H01L 29161

Patent

active

046724133

ABSTRACT:
A bipolar transistor, and a corresponding method for its fabrication, in which the injection efficiency, and therefore the common emitter current gain, is greatly increased without significant increase in the emitter resistance of the transistor. An emitter tunneling barrier is formed within the emitter region of the transistor, rather than at the junction between emitter and base regions, and the emitter region adjacent to the barrier is heavily doped. The heavy doping of the emitter results in an increased injection efficiency, but the barrier is thin enough to preclude any significant increase in emitter resistance. The disclosed device is a silicon transistor and the barrier material is either silicon dioxide or semi-insulating polycrystalline silicon (SIPOS), sandwiched between emitter layers of heavily doped polycrystalline silicon material.

REFERENCES:
patent: 3372315 (1968-03-01), Hartman
patent: 4062034 (1977-12-01), Matsushita et al.
patent: 4131902 (1978-12-01), Kub
patent: 4286275 (1981-08-01), Heiblum
patent: 4302763 (1981-11-01), Ohuchi et al.
patent: 4396931 (1983-08-01), Dumke et al.

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