Patent
1986-12-01
1989-04-04
Edlow, Martin H.
357 231, 357 237, 357 2312, 357 41, 357 239, H01L 2978, H01L 2702
Patent
active
048190438
ABSTRACT:
An MOSFET provided with a gate insulating film formed on a semiconductor surface between a source region and a drain region, a gate electrode formed on the gate insulating film, and a channel region sandwiched between the source region and the drain region and made up of a first layer and a second layer is disclosed in which the first layer lies beneath the gate insulating film and is opposite in conductivity type to the source and drain regions, the second layer lies beneath the first layer and has the same conductivity type as the source and drain regions, and the length of the second layer between the source region and the drain region is greater than the length of the first layer between the source region and the drain region.
REFERENCES:
patent: 3283221 (1966-11-01), Heiman
patent: 3936857 (1976-02-01), Ota
patent: 4000504 (1976-12-01), Berger
patent: 4613882 (1986-09-01), Pimbley et al.
patent: 4636822 (1987-01-01), Codella et al.
IEDM 1978, "A Normally-Off . . . Circuits", by Nishiuchi et al., pp. 26-29.
T. Wada et al., "A Study of Hot. Carrier . . . Device Simulator", presented at the 45th Japanese Applied Physics Conference, Oct. 12-15, 1984.
Fukami Akira
Kobayashi Yutaka
Nagano Takahiro
Yazawa Yoshiaki
Edlow Martin H.
Featherstone Donald J.
Hitachi , Ltd.
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