Output circuit of semiconductor integrated circuit with reduced

Details Output circuit of semiconductor integrated circuit with reduced Output circuit of semiconductor integrated circuit with reduced

1989-05-01

1992-07-07

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307576, 307585, 307602, 307605, 307451, H03K 17687, H03K 513, H03K 19094

Patent

active

051285673

ABSTRACT:
An output circuit of a semiconductor integrated circuit includes a plurality of output transistors having different current driving abilities for a load, and a plurality of signal delay means for delaying signals for driving each of the output transistors by different delay times, wherein the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a first delay time is set to be larger than the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a second delay time shorter than the first delay time.

REFERENCES:
patent: 4700089 (1987-10-01), Fujii et al.
patent: 4719369 (1988-01-01), Asano et al.
patent: 4725747 (1988-02-01), Stein et al.
patent: 4774690 (1988-09-01), Watanabe et al.
patent: 4789793 (1988-12-01), Ehni et al.
patent: 4820942 (1989-04-01), Chan
patent: 4890016 (1989-12-01), Tanaka et al.
Anderson et al., "Investigation of the Performance of Advanced CMOS Output Buffers in a Transmission Line Environment", May 10-12, 1988, 8079 Electro 1988 Conference Record 13, pp. 1-4.

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