Programmable redundancy circuit

Details Programmable redundancy circuit Programmable redundancy circuit

1985-08-29

1987-06-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307441, 307450, 307463, 307468, H03K 19003, H03K 19094, G11C 8000

Patent

active

046722408

ABSTRACT:
A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder.The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.

REFERENCES:
patent: 3886532 (1975-05-01), Wegener et al.
patent: 4041459 (1977-08-01), Horninger

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