Decoding apparatus

Excavating

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Details

360 53, 360 32, G06F 1110, G11B 500

Patent

active

048021725

ABSTRACT:
A decoding apparatus in which the operation to write error correction coded data into a memory and a decoding processing operation of the data read out of the memory are executed in parallel. This decoding apparatus comprises: a comparator for comparing the address to write the data into the memory with the address in the memory for the decoding processing operation; and control means for inhibiting the writing operation when it is detected by the comparator that the decoding processing operation is precedent to the writing operation. With this apparatus, the data which was subjected to the correcting process is prevented from being rewritten into the memory and the pointer derived by the decoding process from being broken.

REFERENCES:
patent: 4446490 (1984-05-01), Hoshimi et al.
patent: 4523237 (1985-06-01), Fukuda et al.
patent: 4622600 (1986-11-01), Okamoto et al.
patent: 4628373 (1986-12-01), Takahashi et al.

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