Method for forming a vertically integrated dynamic memory cell

Details Method for forming a vertically integrated dynamic memory cell Method for forming a vertically integrated dynamic memory cell

1994-04-20

1995-09-19

Chaudhari, Chandra

Gas: heating and illuminating

437 89, 437915, H01L 218242

Patent

active

054515386

ABSTRACT:
A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34). A capacitor (69) is formed overlying and coupled to the vertical transistor (10) in order to form a dynamic random access memory (DRAM) cell.

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