Method of forming a DRAM stack capacitor with ladder storage nod

Details Method of forming a DRAM stack capacitor with ladder storage nod Method of forming a DRAM stack capacitor with ladder storage nod

1994-08-12

1995-09-19

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

054515378

ABSTRACT:
A method, and resultant structure, is described for fabricating a DRAM (Dynamic Random Access Memory) cell having a stack capacitor with a ladder storage node, connected to a MOS (Metal Oxide Semiconductor) transistor with source and drain regions, to form a DRAM cell. A bottom electrode is connected to and extends up from the source region of the transistor, and has a top surface with a central cavity, and side surfaces extending down from the top surface in a step-like manner. These step-like sides are formed by a repeated two-step process of removing a portion of the vertical walls of a photoresist mask and removing a portion of the top surface of a layer of polysilicon from which the bottom electrode is formed. There is a capacitor dielectric over the bottom electrode. A top electrode is formed over the capacitor dielectric.

REFERENCES:
patent: 5183772 (1993-02-01), Jin et al.
patent: 5384152 (1995-01-01), Chu et al.
patent: 5399518 (1995-03-01), Sim et al.

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