Method for forming integrated circuits having buried doped regio

Details Method for forming integrated circuits having buried doped regio Method for forming integrated circuits having buried doped regio

1994-01-11

1995-09-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 26, 437 28, 437 69, H01L 21761

Patent

active

054515300

ABSTRACT:
A method for fabricating an integrated circuit having a buried doped region is disclosed. A thermal oxide layer is formed over a portion of a p-type substrate at which an n+ buried doped region is not to be formed, masking the implant for the buried doped region. Anneal of the implant is performed in an oxidizing atmosphere, growing further oxide over the surface. The oxide layers are removed, and a p-type blanket implant is performed for isolation purposes and, if desired, to form a p-type buried doped region; the doping concentration of the n+ buried doped region retards diffusion of the boron to the surface thereover. Alternatively, a higher than normal doping level in the substrate can provide sufficient boron for isolation. An epitaxial layer is then grown over the surface, and the n-well is formed by implanting n-type dopant, with the p-well regions masked by a nitride mask; anneal of the n-well is also done in an oxidizing environment, so that consumption of a portion of the n-well by the oxide further planarizes the topography of the device.

REFERENCES:
patent: 4373252 (1983-02-01), Caldwell
patent: 4761384 (1988-08-01), Neppl et al.
patent: 4835115 (1989-05-01), Eklund
patent: 4840920 (1989-06-01), Suda
patent: 5310690 (1994-05-01), Bell et al.

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