Patent
1990-09-24
1992-02-18
Hille, Rolf
357 34, 357 36, 357 20, 357 43, H01L 2906, H01L 2972, H01L 2702
Patent
active
050898736
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device comprising a semiconductor body with an integrated circuit having a vertical transistor comprising a collector zone of a first conductivity type, a base region of a second conductivity type disposed on at least a part of the collector region and an emitter region comprising at least one zone of the first conductivity type included in a part of the base region adjoining a major surface of the semiconductor body.
In known bipolar transistors, the inverse current amplification .beta..sub.I defined as the ratio between the emitter current I.sub.E and the base current I.sub.B when the collector-base junction is polarized in the inverse sense is usually not very high.
However in certain applications, it is desirable to have available transistors having a high inverse current amplification .beta..sub.I of, for example several tens. In that case, it is possible to improve the collector-base voltage V.sub.CEsat of the transistor in saturation or, whilst utilizing the transistor in the inverse sense, to realize a multi-collector transistor.
SUMMARY OF THE INVENTION
The invention has for its object to provide for a semiconductor device comprising an integrated circuit with such a vertical transistor.
The invention is based on the recognition that, in case the overall thickness of the base is smaller than or equal to the diffusion length of the minority charge carriers in this region, the phenomena of injection of charge carriers obey quite different rules from those admitted by the conventional theories.
According to the invention a semiconductor device of the kind described above paragraph is characterized in that the overall thickness of the base is smaller than or equal to the diffusion length of the minority charge carriers in this region, in that the base region comprises at least one base contacting zone having at least one contact area adjacent to the said zone of the emitter region, this base contacting zone being covered by an isolating layer having a window, through which a contact is provided to the contact area, the ratio between the surface area of the base contacting zone and the surface area of the window being at least equal to 10, and in that the base contacting zone has a surface area smaller than 5 times the total surface area of the emitter region.
These dimensional ratios assure the realization of amplification values which are interesting in practice. More particularly, and paradoxically, said contact provides an improvement of the amplification which is more striking in proportion as its area in contact with the contacting zone is smaller.
According to a first embodiment, the base contact area is enclosed by a unique zone constituting the emitter region.
According to a second embodiment, the emitter region has at least two zones enclosing at least one surface of the said base contacting region.
According to a third advantageous embodiment, the emitter region has at least two pairs of zones, the two zones of one pair enclosing a surface of said base contacting region.
According to a preferred embodiment, the base region has a plurality of branches, each branch comprising a zone of the emitter region, while the base contact area is disposed in a central region with respect to the branches.
BRIEF DESCRIPTION OF THE DRAWING
The invention will be more clearly understood after reading the following description given by way of non-limitative example in conjunction with the drawing in which:
FIGS. 1a and 1b show in plan view and in sectional view, respectively, a first embodiment of the invention;
FIGS. 2a and 2b show in plan view and in sectional view, respectively, a second embodiment of the invention;
FIGS. 3a and 3b show a preferred embodiment of the invention; and
FIG. 4 shows a third embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
According to FIGS. 1a and 1b, an integrated circuit in accordance with the invention comprises a p-type substrate 1, on which a buried n.sup.+ layer 5 forming the
REFERENCES:
patent: 4686557 (1987-02-01), Mahrla
Biren Steven R.
Fahmy Wael
Hille Rolf
U.S. Philips Corp.
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