Semiconductor memory device with improved groove capacitor

Details Semiconductor memory device with improved groove capacitor Semiconductor memory device with improved groove capacitor

1991-04-02

1992-02-18

James, Andrew J.

357 51, 357 55, 357 59, H01L 2968, H01L 2702, H01L 2906, H01L 2904

Patent

active

050898680

ABSTRACT:
A semiconductor memory device which is provided with a groove type capacitor and which has been improved for increasing its storage capacity without lowering the degree of integration, and the method for producing the memory device. The device includes a first capacitor including a storage node (16) formed on the inner wall of the groove (15), a capacitor insulating film (20) and a cell plate electrode (22), a second capacitor including an electrically conductive member (43) provided on the perimeter of the groove (15), the capacitor insulating film (20) and the cell plate electrode (22). The semiconductor memory device has its storage capacity increased by an amount corresponding to the capacity of the second capacitor. The degree of integration is not lowered in any way since the electrically conductive member (43) forming the second capacitor is provided on the groove (15) perimeter. The method for producing the semiconductor memory device is improved such that high accuracy mask matching is not required during groove (15) formation so that the production efficiency is significantly improved.

REFERENCES:
patent: 4646118 (1987-02-01), Takemae
patent: 4835589 (1989-05-01), Pfiester
patent: 4845539 (1989-07-01), Inoue
patent: 4894696 (1990-01-01), Takeda et al.
patent: 4896197 (1990-01-01), Mashiko
patent: 4899203 (1990-02-01), Ino
patent: 4914739 (1990-04-01), Malhi
"High Density Memory Cell Structure With Two Access Transistors", IBM Technical Disclosure Bulletin, vol. 31, No. 7, Dec. 1988, pp. 409-414.

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